Following up to “SystemVerilog — always blocks are needed less and less“, which had an example of an assignment that should have been legal, but wasn’t.
Until now it hasn’t been legal to make a nonblocking assignment (NBA) to a static module variable across a reference port of a function or task. But in the 2023 revision of the standard that restriction has been lifted as long as the reference port has been annotated with the new static qualifier. Thanks to Steven Sharp for driving that enhancement. His enhancement also lifted the restriction against referring to such ports from within a fork–join_any or fork–join_none block, again given the new static qualifier.
So here’s the earlier example modified to be legal in SystemVerilog 2023
virtual class C#(type T);
static task ff(const ref logic clk,
const ref T in,
ref static T out);
forever @(posedge clk) out <= in;
endtask
endclass
module test#(type T) (input logic clk,
input T in,
output T out);
initial C#(T)::ff(clk, in, out);
endmodule
In the settlement between Rossi and his US licensee IH, Rossi got the license back together with all E-Cat equipment and materials, while none of the parties will have to pay damages to the other. Getting the license back was his top priority all the time, Rossi explains in this interview.
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