SV23: Nonblocking assignment across a task ref port

Following up to “SystemVerilog — always blocks are needed less and less“, which had an example of an assignment that should have been legal, but wasn’t.

Until now it hasn’t been legal to make a nonblocking assignment (NBA) to a static module variable across a reference port of a function or task. But in the 2023 revision of the standard that restriction has been lifted as long as the reference port has been annotated with the new static qualifier. Thanks to Steven Sharp for driving that enhancement. His enhancement also lifted the restriction against referring to such ports from within a fork–join_any or fork–join_none block, again given the new static qualifier.

So here’s the earlier example modified to be legal in SystemVerilog 2023

virtual class C#(type T);
  static task ff(const ref logic clk,
                 const ref T in,
                 ref static T out);
    forever @(posedge clk) out <= in;
  endtask
endclass

module test#(type T) (input logic clk, 
                      input T in,
                      output T out);
  initial C#(T)::ff(clk, in, out);
endmodule

SV23: Terms ‘master’ and ‘slave’ purged from next revision of SystemVerilog standard

In December 2020, the IEEE SA Standards Board resolved, “IEEE standards should be written in such a way as to avoid non-inclusive and insensitive terminology (see IEEE Policy 9.27) and other deprecated terminology (see clause 10 of the IEEE SA Style Manual) except when required by safety, legal, regulatory, and other similar considerations. Terms such as master/slave, blacklist, and whitelist should be avoided.”

John Byler in “What Is the Best Way to Purge Master and Slave Terms From Engineering Documents?” lists some proposed replacements, such as “initiator-target”, and writes

“Whatever terminology replaces master-slave, the critical matter is that a far less degrading alternative is agreed to and implemented as soon as possible.”

A special thanks should go to Don Mills, the SystemVerilog trainer and one of the driving participants in the 2023 revision of the standard, who was the first to raise this issue in the committee.

The SV23 committee eventually went with the “initiator-target” replacement terminology.

SystemVerilog 2023

The IEEE working group for the SystemVerilog standard will restart on 21 January 2021.

It’s an entity-based standard, so to engage in the discussions you must represent a participating corporate member of the IEEE Standards Association.