In a SystemVerilog design many basic types and sizes are shared. Passing them down as Verilog-style module parameters through endless levels of instantiation hierarchy isn’t the best way to keep SystemVerilog module definitions generic.
SystemVerilog added two lexical scoping mechanisms beyond module definitions for this purpose, the compilation-unit scope (
$unit) and packages. I recommend packages.
An old objection that is no longer accurate was that types and sizes from packages could not be used in the declarations of module ports without either fully qualified package references (such as
type_package::T) or wildcard imports into
$unit. But that was fixed in IEEE Std 1800-2009 by allowing package imports directly after the module name in a definition.
A new objection is that package imports after the module name clutter up the code, because if they are sharing global types and values they are needed in almost every module and interface definition. But here I show an easy way to get rid of the clutter with an unobtrusive macro.
`define _ import global_parameters::*, type_package::*; module test `_ ( input var T in[N] , output var T out[N] ); always_comb out = in; endmodule