Type-checking SystemVerilog interfaces using a class signature

As I wrote here,

Unlike class specializations, interface specializations cannot be used in a module port declaration. For example, the following is disallowed

module m #(parameter N) (IFC#(N) ifc, ...);

Steven Sharp followed up here that perhaps it was an oversight instead of a decision. Either way, it is still disallowed. He discusses some of the problems this causes for separate compilation. Happily, it is possible to get the effect of at least type checking SystemVerilog interfaces by combining class specializations (8.25) and interface-based typedefs (6.18) using a couple macros.

`define SIGNATURE_DEFINE(Params) \
   typedef SIGNATURE Params \%SIGNATURE ;

`define SIGNATURE_CHECK(Params, Port) \
  if (1) begin \
    typedef SIGNATURE Params Expected; \
    typedef Port.\%SIGNATURE Actual; \
    if (type(Expected) != type(Actual)) begin \
      $fatal("Mismatch"); \
    end \
  end 

Here’s a simple example

virtual class SIGNATURE#(int N, type T);
endclass

interface IFC#(int N, type T);
  `SIGNATURE_DEFINE(#(N,T));
  T a[N], z[N];
  modport mp (input a, output z);
endinterface

module top;
  IFC#(8,int) ifc_inst();
  test#(32,byte) test_inst(ifc_inst.mp);
endmodule

module test#(int N, type T)(IFC.mp ifc_mp);
  `SIGNATURE_CHECK(/*IFC*/#(N,T), ifc_mp);
  // ...
endmodule
Copyright © 2016 Brad Pierce
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1 Comment

  1. Thanks Brad, that’s intriguing, a coding pattern that could be useful elsewhere too. Unfortunately it’s not very useful just now, as vendor support for the type() operator is – how shall we say – patchy.

    Could you, as a compiler guy, comment on whether the creation of large numbers of virtual class typedef specializations could be a significant overhead for elaboration?

    Like

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