Waveform debugging 2015

According to Dave Rich in “A Decade of SystemVerilog: Unifying Design and Verification?

Most design engineers still debug their simulations the same way they debug in the lab: they look at waveforms. During simulation, they rarely look at the design source code, and certainly never look at the testbench code (unless it’s just basic pin wiggling like a waveform). Verification engineers are not much different. They rely on waveform debugging because that is what they were brought up on, and many do not even realize source-level debugging is available to them.

Vital signs

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2 Comments

  1. Design source can be very useful for debugging, however, the simulation tool I use (one of the biggest vendors) does a very bad job at enabling systemverilog class debugging, especially within functions.

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  2. “Innovation is a change of practice that displaces other practices already in place. Inventing creative technology does nothing: people must take up new practice.”

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