In SystemVerilog design, ‘unique case () inside’ should be your default ‘case’

I recommend requiring the following macro instead of direct uses of  case or casex

`define CASE(EXPR) \
   unique case (EXPR) inside

except when there’s a strong justification for the more expensive alternative

   priority case (EXPR) inside

If, as usual, the expectation is that every value should find a match, or if there is a default branch, then close with

`define ENDCASE \

But if the intent really is for some values not to match any case items, and there is no default branch, then close with



  1. Argh! Don’t create an obtuse macro just to save a few keystrokes. If you want to use unique case inside, then use it and create a linter rule to check for it.


    • Life would be easier for me without the “beast that Verilog macros have become”, but a few keystrokes is a major reason why VHDL never got ASIC traction in California/India.


  2. If there is a default branch or if you add a default branch, then there is no point to ‘priority’, it will have no effect.


    • Yes, but if you always (and only) use ‘priority’ when it’s not a parallel case, then it highlights syntactically that priority logic will be inferred. And I claim that using priority logic ought to require a justification.


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