INVITATION: Celebrate 10 Years of IEEE 1800™ SystemVerilog – 14 October 2015 – San Jose, CA USA

Forwarding an invitation for

WHAT: Celebrate 10 Years of SystemVerilog
DATE: 14 October 2015
TIME: Noon-2PM Celebration and Open Discussion
LOCATION: Cadence Design Systems, Building 10, 2655 Seely Avenue, San Jose, CA 95134
FREE REGISTRATION: Click here

According to the invitation

We invite all who have worked to create SystemVerilog from the beginning days of Accellera to the first IEEE version to the most recent revision in 2012 to come together to celebrate and discuss the next steps in further standardization.

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