Because it’s so common to assign a signed integer constant to a Verilog parameter
parameter SIZE = 8;
a myth has arisen that there is a default signed integer parameter type in Verilog.
But there is no default parameter type in Verilog. The type of a parameter (or a local parameter) is the type of whatever value is eventually assigned to it during elaboration. Override
SIZE above with
"four score and seven years ago" and its type becomes an unsigned vector of width 240.
Verilog 2001 (IEEE Std 1364-2001) added the ability to write
parameter integer SIZE = 8;
so that the right-hand side would instead be evaluated in the context of an assignment to a parameter of type
integer. But that never caught on, because apparently it’s considered too painful to write
integer after every
(An extra complication is that Verilog also has some half-way specifications you can add to parameters. For the horrible details, see the bottom of p. 694 in IEEE Std 1800-2012.)
When SystemVerilog extended the Verilog type system, it allowed any of those new types to be used after
parameter. Most importantly here, it added an
int type that is a 2-state version of
If you are confident it’s only going to be a simple signed integer parameter value, such as #(.N(8)), then I guess even in SystemVerilog you could go ahead and still omit the explicit type from the
parameter declaration, because it’s too painful to write the three extra characters
int after every
But if I personally were defining a SystemVerilog coding guideline, I would insist on
parameter int N = … or some other explicit type, instead of letting it depend on the type of the value.
parameter int SIZE = 8;