SVA (SystemVerilog assertions) standards sub-committee to meet 18 November 2014 via audio conferencing

Update: The minutes are here. According to them

The general opinion at the last IEEE P1800 WG meeting was to have a “quiet” PAR with minimal number of changes. Main exceptions: work required to merge Verilog-AMS with SystemVerilog (mostly belongs to SV-DC subcommittee), and work required to support the standardization of UVM (P1800.2; mostly belongs to SV-EC subcommittee).

According to this invitation, the SV-AC will meet 1700 UTC on 18 November 2014 (via audio conferencing) to prepare recommendations for the scope of a revision Project Authorization Request (PAR) for P1800.

As discussed here, a meeting of the full P1800 will probably be scheduled in or around the March 2015 DVCon in Silicon Valley. But, in the meantime, sub-committees are free to meet to prepare their recommendations about scope.

Because the P1800 uses the IEEE-SA “Entity Standards Development Process”, any employee of an IEEE-SA Advanced Corporate Member is eligible to participate in the 18 November meeting.


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