Don’t use X assignments to make SystemVerilog case statements more pessimistic

According to Stuart Sutherland (paper, slides)

The best way to handle X problems is to detect the X as close to its original source as possible. This paper has shown how SystemVerilog assertions can be used to easily detect and isolate design bugs that result in an X. With early detection, it is not necessary to rely on X propagation to detect design problems.

and

10.3. X-assignment guidelines

Using X assignments to make if…else and case statements more pessimistic should not be used. They add overhead to simulation, and can simulate differently than the logic that is generated from synthesis. The pessimistic X propagation can lead to false failures that can take time to debug and determine that there not be a problem in actual silicon. In lieu of using pessimistic coding styles to propagate X values, problems should be trapped at the select condition, as shown in Section 9, and discussed in the following guideline.

10.4. Trapping X guidelines

All RTL models intended for synthesis should have SystemVerilog assertions detect X values on if…else and case select conditions. Other critical signals can also have X-detect assertions on them. Design engineers should be responsible for adding these assertions. Section 9 showed how easy it is to add X-detecting assertions.

Advertisements

Tell me (anonymous OK)

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s