How to slice a SystemVerilog interface

A synthesizable interface coding example connecting a server to 16 clients. The server is passed a large interface with 16 pairs of request and response words, and each client is passed a small interface that gives access to only one pair. This is done by first passing the big interface to each of the small interfaces, and then passing the small interfaces to the clients using a modport that restricts access to just one pair.

localparam type requestType = byte;
localparam type responseType = int;

module testMod#(N=16);

  wire clk, rst;

  allIfc#(N) allInst(clk, rst);
  serverMod#(N) serverInst(allInst.serverMp);

  for (genvar I = 0; I < N; I++) begin:GEN
    sliceIfc#(I) sliceInst(allInst.clientMp);
    clientMod clientInst(sliceInst.clientMp);


interface automatic allIfc#(N=0)(input clk, rst);

  var requestType Requests[N];
  var responseType Responses[N];

  function requestType requestRead(int index);
    return Requests[index];

  function void responseWrite(int index, responseType response);
    Responses[index] <= response;

  modport clientMp(output Requests, input Responses,
                   input clk, rst);

  modport serverMp(input Requests, output Responses,
                   import requestRead, responseWrite,
                   input clk, rst);


interface automatic sliceIfc#(I=0)(allIfc.clientMp allInst);

  var requestType request;
  var responseType response;

  assign allInst.Requests[I] = request;
  assign response = allInst.Responses[I];

  function void requestWrite(requestType req);
    request <= req;

  function responseType responseRead();
    return response;

  wire clk = allInst.clk;
  wire rst = allInst.rst;

  modport clientMp(output request, input response,
                   import requestWrite, responseRead,
                   input clk, rst);


module clientMod(sliceIfc.clientMp sliceInst);
  // ...

module serverMod#(N=0)(allIfc.serverMp allInst);
  // ...

Copyright © 2014 Brad Pierce


  1. Thanks for your reply but I guess there is no need for bug report because I meant to say I am getting DCELAB-914, your suggestions/comments are welcome


    • Don’t use “read_sverilog”. Use “analyze -f sverilog; elaborate testMod”.


      • Yes you are right to the point, absolutely 100% the code is synthesizing, I should have known this command before.


  2. Hi Brad,

    I guess allInst.Requests will become multiple driven?



    • allInst.Requests is an unpacked array of bytes. Each of those elements is driven by only one client. Consider a particular word like allInst.Requests[5].


      • yes, I agree but if I understood correctly allInst.Requests[0][7]….[0] and then allInst.Requests[1][0]… will be multi dimensional unpacked array, still i could not figure that why I get 914 error, is that possible because of values does not match from first to last.


        • Hi Vijay, the test case as written is legal and accepted without complaint by the tools I have access to. So if you are using a tool that issues an error when elaborating testMod, on the test case as written, then it’s time for a bug report to that tool.


  3. i want to learn system verilog, now i am studying M.E VLSI DESIGN, i have just studied about verilog only, can you please guide me sir


    • Siva Raj, the clause overviews (such as 25.2) in IEEE Std 1800-2012 are a good starting point, because the standard is written in a style that attempts to be readable instead of formal and legalistic. Click on the bar graph in the preceding blog entry for download instructions. (It is free.)

      Then try to find a copy of the “SystemVerilog for Design” book , which hopefully is in one of the Educational Hub libraries. Click on the book cover and you will find (near bottom) a link for free download of the examples in its first edition.


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