More SystemVerilog enhancement requests for design

Following up to “SystemVerilog — my top 10 enhancement requests for design“.

  1. Subtype of singular type using inside operator and typedef ()
  2. Generalize “?:” operator with “case ?” operator ()
  3. Allow object method calls to be deferred to NBA region ()
  4. Prohibit defparam to elements of arrayed instances, and allow dynamic indexing of arrayed instances ()
  5. Prohibit parameters in subroutines and blocks, and treat parameter keyword there as synonym for localparam ()
  6. Allow member_identifier in lvalue assignment patterns ()
  7. Positional assignment pattern on both sides, ‘{lval1, lval2, lval3} <= '{rval1, rval2, rval3} ()
  8. Type parameter allow as much restriction as a forward typedef ()
  9. `define_system to escape preprocessor into system call ()
  10. Remove ‘generate’ keyword and prohibit ‘genvar’ outside a genvar_initialization ()
  11. Optional compile-time error for unnamed generate blocks of 27.6 ()
  12. Directive to prevent implicit signed to unsigned operand demotion ()
  13. Enumeration method enum() that returns value of enum ()

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