According to Michael B. Taylor in “A landscape of the new dark silicon design regime”
Increasingly over time, the semiconductor industry is adapting to this new design regime, realizing that multicore chips will not scale as transistors shrink and that the fraction of a chip that can be filled with cores running at full frequency is dropping exponentially with each process generation. This reality forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark — either idle for long periods of time or significantly underclocked. As exponentially larger fractions of a chip’s transistors become darker, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift calls for new architectural techniques that “spend” area to “buy” energy efficiency. This saved energy can then be applied to increase performance, or to have longer battery life or lower operating temperatures.
The way forward may be to learn lessons from biological brains, such as severely limiting multiplexing and
Fast, static, “gather, reduce, and broadcast” operators. Neurons have fan out and fan in of approximately 7,000 to other neurons that are located significant distances away. Effectively, they can perform efficient operations that combine vector-style gather memory accesses to large numbers of static-memory locations, with a vector-style reduction operator and a broadcast. Do more efficient ways exist for implementing these operations in silicon? It could be useful for computations that operate on finite-sized static graphs.