SystemVerilog — passing a set as a module parameter

Although there is no built-in set type in SystemVerilog, if the set is an elaboration-time constant, as needed for a module parameter, then an unpacked array and the inside operator can get the job done.

For example, if

typedef enum {bronze, silver, gold} ET;
localparam ET P[2] = '{silver, gold};

then the following yields true

gold inside {P}

and the following yields false

bronze inside {P}

One use of passing a set would be to prune back a powerful, generic machine module to just those instructions that will actually be needed by the intended application. For example, the machine module could be defined using a guarded case

case ((inst inside {INST_SET}) ? inst : NO_OP )
   ...
endcase

A tool could then notice at elaboration-time that some case branches are unneeded for that instance, under the full control of the user of the machine module, even when the definition of the machine module is encrypted by its owner.

You can also use unpacked arrays to pass some constant functions as lookup tables, but you need to find a 1-1 mapping from the input type of the function to the integers that are required as indices. For example,

function automatic out_t f(in_t in);
  return LUT_parameter[mapping(in)];
endfunction

SystemVerilog has a built-in type, associative arrays, for lookup tables, but in SV12 they still can’t be passed as elaboration-time module parameters. When that’s fixed in some future revision, it will be possible to just write

LUT_parameter[in]

for an associative array parameter and have tools take care of the details.

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