SystemVerilog — my top 10 enhancement requests for design

  1. Nondeterministic choose_inside operator ()
  2. Untyped module port ()
  3. Module passed down like parameter ()
  4. Parameterizable package ()
  5. ‘let’ statement ()
  6. ‘let’ class method ()
  7. NBA to static module variable by reference ()
  8. Extern module/interface in package ()
  9. Tool-specific header file distribution with `include ()
  10. generate ‘foreach’ loop ()

For a few more ideas, see here.

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