Why does Verilog use additional named wires to connect adjacent instances?

In Verilog, when two modules are composed by directly connecting their ports, why is the tradition to declare a wire in the parent and connect the ports indirectly through it? For example, why not as follows?

module buffer(input in, output out);
  assign out = in;
endmodule

module test(input in, output out);
  buffer child1(.in ),
         child2(    ),
         child3(.out);
  assign child2.in = child1.out;
  assign child3.in = child2.out;
endmodule

Or, equivalently

module buffer(input in, output out);
  assign out = in;
endmodule

module test(input in, output out);
  buffer child1(.in),
         child2(child1.out, child3.in),
         child3(.out);
endmodule

Either of those look more naturally like the sketch you’d start coding from. The extra level of indirection of a named wire in the parent doesn’t seem to add anything. Maybe it’s rare in practice to directly connect modules without intervening logic?

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2 Comments

    • Shalom, I’m wondering about the reasons for tradition here. The limitation of old synthesis tools against accepting hierarchical references is just a tradition, because they are clearly synthesizable in principle. And in the example I gave, there is no wire, because pins from abutting instances are identified with each other.

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