SystemVerilog — cell arrays and the >> streaming operator

When connecting up array of instances of modules that have only single-bit ports (such as a flip-flop), often all you care about is that the port expressions have an equal number of bits. The types could be anything, packed or unpacked, and not necessarily the same on each port.

The generic way to write this is with an extra level of hierarchy and the >> streaming operator of 11.4.14. For example,

     U( .D({>>{rvalue}}) 
      , .CLK(clock)
      , .Q({>>{lvalue}})


  module DFF_array#(N)
  ( output [N-1:0] Q
  , input CLK
  , input [N-1:0] D
    DFF U[N](.*);

A side-benefit of the extra level of hierarchy is that you can iterate over the output bits with a regular procedural loop (such as ‘foreach’ of 12.7.3), unlike the output bits from the individual instances, which you could only iterate over with a generate for-loop.


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