SystemVerilog synthesis — building designs bottom-up

Useful, short advice from Synopsys HERE with example. (Behind a password for customers only.)

Question:

How do I use a bottom-up approach to build a SystemVerilog design that uses type parameters or interfaces with parameters?

Answer:

Advertisements

Tell me (anonymous OK)

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s