SystemVerilog — getting the effect of generated case items

You can’t generate case items in SystemVerilog, but you can sometimes get the same effect by hand-generating a very large case statement that can handle all the sizes you’ll actually need. For example, suppose you’ve decoded an index and want to use that one-hot vector to select from an array.

virtual class C#(type T_array, T_index, T_result);
  localparam N = 128;
  static function logic select(
       input T_array A, input T_index idx,
       output T_result result
    );
    typedef logic [N-1:0] T;
    unique case (T'(idx))
      1'b1 <<   0: result = A[  0];
      1'b1 <<   1: result = A[  1];
      1'b1 <<   2: result = A[  2];
      // ...
      1'b1 << 125: result = A[125];
      1'b1 << 126: result = A[126];
      1'b1 << 127: result = A[127];
    endcase
    return 0;
  endfunction
endclass

let select(A, idx, result) = 
    C#(type(A), type(idx), type(result))::
    select(A, idx, result);
Advertisements

Tell me (anonymous OK)

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s