SV12 — how much distance from SystemVerilog to SystemC?

Now that SV12 has channels/interfaces, what’s left that sets SystemC significantly apart as a system-level modeling language?

According to Sergey in the comments below

The first thing that directly comes to my mind (without thinking thoroughly) is the absence of SV compilers (to executable machine code). This normally prevents a system designer from maintaining the complete chain of a system design (refinement of a model from high-level aspects(including system partitioning) to implementation-level aspects). A system designer has to decide which part of computations is good (possible, feasible) for a Processing Unit(s) (uC/uP), and which part is good for configurable logic. Thus a more universal approach is in using a C-language. Benefits are: 1) fast simulation of a complete system in exe-code; 2) no need to recode SV->C(++) for uC part (it is easier to recode a part of a project from C(++) to SV if it proves to be efficient on an FPGA, than to recode SV to C++ if it fails totally on configurable logic).
From the syntax side I do not see problems with SV directly, because for me the SV is a HW flavour of Java (roughly speaking).

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2 Comments

  1. The first thing that directly comes to my mind (without thinking thoroughly) is the absence of SV compilers (to executable machine code). This normally prevents a system designer from maintaining the complete chain of a system design (refinement of a model from high-level aspects(including system partitioning) to implementation-level aspects). A system designer has to decide which part of computations is good (possible, feasible) for a Processing Unit(s) (uC/uP), and which part is good for configurable logic. Thus a more universal approach is in using a C-language. Benefits are: 1) fast simulation of a complete system in exe-code; 2) no need to recode SV->C(++) for uC part (it is easier to recode a part of a project from C(++) to SV if it proves to be efficient on an FPGA, than to recode SV to C++ if it fails totally on configurable logic).
    From the syntax side I do not see problems with SV directly, because for me the SV is a HW flavour of Java (roughly speaking).

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