A major SV12 productivity gap is the lack of a standard way to express the most common design concepts. For example, many designs use leading-zero detectors or priority encoders, yet everybody must write these well-understood old ideas again and again, or at best instantiate them from whatever IP library is being used locally.
It would be a major contribution to the SystemVerilog community for someone to define a standard collection of design packages and modules. (A modest initial version to get the ball rolling might be feasible as a student project?)
A secret to making it work would be resisting the temptation to provide a reference implementation. According to Brian Bailey
The other problem for the EDA companies — and this has been a consistent problem with SystemC — is that there are reference implementations. This makes it a lot more difficult for an EDA company to provide the necessary investment and to get a return from it. The market expects a price of zero and that means no incentive for the EDA companies to provide support.
A reference executable SVA specification might be nice to have though.