SV12 — good-bye modules, hello object-oriented design

There are some obvious advantages vs. Verilog modules of the object-oriented descriptions of SV12. Classes are true types supported by the full modern toolbox of inheritance, interfaces, and virtual methods.

Instead of always blocks, an object-oriented hardware description in SV12 would use forever-methods that are forked off at time-0 by the constructor in the style of 13.4.4.

For arrays of class objects, you wouldn’t be hobbled, as you are for arrays of instances and generate-for scopes, by a restriction against dynamic indexing, because you’d be liberated from defparam. (See C.4.1.)

What would you lose today by laying things out at time-0 instead of at elaboration time? (“Today”, because it’s possible that a future revision of the LRM could recuperate them for time-0.) The only Verilog things that come to mind are configurations and conditional generate.

For SV12, there are probably various restrictions left to cope with, such as footnote A.10.11 about package imports.

But it’s not as if we must purge modules entirely. They would still be needed at least at the boundaries, such as for initial blocks that construct the highest-level objects and for the generic interconnect used in discrete real modeling.

Aside: According to Malcolm Gladwell, “If everyone has to think outside the box, maybe it’s the box that needs fixing.”


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