In reading the SV12 LRM, beware the second example in 25.5.4, which has regrettably been passed down from earlier revisions. The concept of generated modports doesn’t make much sense to me, at least as it is now defined. (I tried to find a better semantics HERE.)
When you hear the siren song of generated modports, head for arrays of modports instead.
By an “array of modports”, I mean imposing a modport on an array of instances when it’s passed, such as “bot bot(inst_array.mp);”, where mp is a modport for that kind of instance. That is, the modport is imposed on each instance in the array as the array is passed.
Two related entries
- In SystemVerilog arrays of interfaces are in some ways more powerful than generate.
- Bus fabric design in SystemVerilog.
In the long-run, I predict the SV community will move to interface classes and channels. But as Keynes said, “The long run is a misleading guide to current affairs. In the long run we are all dead.” So figuring out the best ways to use modports is still important.