The main enhancements in SV12 (IEEE Std 1800-2012)
- Discrete real modeling. For context, start here. Generic (typeless) nets and ports with the new interconnect keyword. User-defined resolution functions with the new nettype keyword.
- Java-style interface classes. According to Wikipedia, “Interfaces are used to encode similarities which the classes of various types share, but do not necessarily constitute a class relationship. … [You can use] an object without knowing its type of class, but rather only that it implements a certain interface.” (As discussed HERE, don’t confuse traditional SV ‘interface’ and the new SV12 ‘interface class’.)
- Checkers more like modules. Output arguments, conditional/looping statements, immediate assertions, task enables, let declarations, and continuous assignments to checker variables.
- More data types in assertions. Reals, queues, dynamic/associative arrays. But not class objects.
- Very deferred immediate assertions. assert final replaces assert #0 (which will be maintained for backward compatibility). assert final does not mature until the Postponed region.
- Constraint-driven test
- Uniqueness constraints. Reuses the unique keyword in constraints to instruct randomization that each in a group of variables should get distinct values.
- e-style soft constraints. Like “keep soft” in e with the new soft keyword.
- Programmable bin construction. According to Dave Rich, “the most important enhancement for testbench writers”. Start with the blue text in this original proposal.