In SystemVerilog RTL design, you’re better off avoiding explicit interface names in port declarations, and instead only using the generic ‘interface‘ keyword.
module test(interface.MP ifc, ...); ... endmodule
A pair of modports is like a pair of plugs at the two ends of a cable. As long as the modports conform to standard APIs, the modules connected across them shouldn’t care which kind of interface instance gets passed in as the implementation.
An interface, for each of its two modports, declares some signals and an always block, plus it declares some cable-like internal signals to connect the two always blocks.
For example, an always block for a modport could be a little finite-state machine that a module reads from and writes to with API function calls as provided by that kind of modport. The FSM would provide the standard level of service for that kind of modport, such as waiting for a response from a shared resource, or queuing up requests, and so on. The particular interface implementation chosen to provide that service should not matter to the module.
If in the abstract, the object doesn’t look like a glorified cable with a modport plug on each end, then it’s not a job for an interface. For example, a computer bus is a complicated module that would have many modports plugged into it. It would be passed many interface instances, but would not itself be an interface.