Bus fabric design in SystemVerilog

If you are a SystemVerilog designer, then I recommend you study a recent short tutorial by my colleague Mahesh Rattehalli, showing a practical methodology for arrays of interfaces.

Creating a Bus Fabric Design in SystemVerilog (Access restricted to Synopsys customers.)

A bus “fabric” or “mesh” is a complex interconnect with its own control logic, such as among an arbiter and an array of client modules.

A key point to keep in mind is that the SystemVerilog standard does not allow the dynamic indexing of arrays of interfaces, but the same effect can be achieved with generates.


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