SV12 — What’s in store for SystemVerilog-2012?

Update May 2012: The standard is on-track for final approval in 2012. Balloting raised no serious objections, so the following list of SV12 enhancements can be safely relied on.

An initial draft of the upcoming IEEE Std 1800-2012 will be completed before the end of 2011. Although theoretically anything could happen during the rounds of balloting that will take place during 2012, I think it’s already safe to predict the big picture of what will be added by SV12.

  • Discrete modeling. For context, start here. Generic (typeless) nets and ports with the new interconnect keyword. User-defined resolution functions with the new nettype keyword.
  • Checkers more like modules. No net declarations yet, but there will be output arguments, conditional/looping statements, immediate assertions, task enables, let declarations, and continuous assignments to checker variables. Also, in checkers old-style always will be replaced with always_[comb,ff,latch].
  • Very deferred immediate assertions. The assert #0 syntax will be maintained for backward compatibility, but will be mostly replaced in practice with assert final, which will not mature until the Postponed region.
  • More data types in assertions. Reals, queues, dynamic/associative arrays. But not class objects.
  • Uniqueness constraints. Reuses the unique keyword in constraints to instruct randomization that each in a group of variables should get distinct values.
  • Java-style interface classes. Classes can implement multiple protocols to get most of the benefits of multiple inheritance, as discussed here.
  • e-style soft constraints. Like “keep soft” in e with the new soft keyword.
  • Programmable bin construction. According to Dave Rich, “the most important enhancement for testbench writers”. (The proposal.)

A big request that you won’t get in SV12: aspect-oriented programing (AOP).



  1. Hi,
    What is the status of ease of Interfaces connections : Top-Bottom splitted interfaces, interface hierarchy , interface inheirtance and multiple inheritance and “on-the-fly” modports (add new standalone modports outside the interface declaration)?


  2. Hi Brad,
    I heard that Verilog-AMS will be also part of System Verilog 2012, but I did not see this in your list. Do you have any idea how Verilog-AMS will be integrated with System Verilog? Will it be a different LRM?



    • There was an effort in Accellera ( ) to produce a SV-AMS based on SV-2009, and the folks doing that were consulted about discrete modeling by the IEEE working group (see first bullet above), but there’s no direct connection between IEEE SV-2012 and the work by Accellera to create an SV-AMS.


    • Updated. Thanks, Dave. It would be a promising topic for your blog.


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