SystemVerilog constant arrays (ROMs)

I still see antique Verilog-style constant arrays in SystemVerilog designs, even though SystemVerilog has a much cleaner way to get that job done. The Verilog way was to declare an array of wires and generate continuous assignments to each of its elements.

The SystemVerilog way is to simply use a constant array. Here’s a nonsense toy example of the modern style

module test#(parameter type B=int , parameter N=3, M=5);
typedef B T[N][M];
const T my_array = fill_my_array(); function T fill_my_array(); for (int i = 0; i < N; i++) begin for (int j = 0; j < M; j++) begin fill_my_array[i][j] = i*j; end end endfunction
// Doing the right thing? initial begin for (int i = 0; i < N; i++) begin for (int j = 0; j < M; j++) begin B temp; temp = i*j; $display("%d %d", temp, my_array[i][j]); end end end


  1. Better yet, make the array a parameter instead of a const, then you can index into elements of the array when using a generate for-loop, or any other place you need constant expressions.



      • The set of functions callable at time 0 is larger than the set of constant functions, and more is known about the design at time 0. Unless the ROM values need to control generate unrolling or to be passed in as parameters to an instantiation, then const arrays are a more general solution.


        • I disagree with anonymous. The set of expressions where you can use a parameter is much larger than than where you can use a const variable. So, if you have the choice, a parameter is preferable because it can be used in more places than a const variable. Only if the initialization expression cannot be made into a constant function should you use a const variable, which is not the case in the example above.


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