Spacetime from Tabula — the next big thing?

Update: According to EETimes, Intel has agreed to be Tabula’s foundry provider, and this “was one of the reasons that Tabula was able to close $108 million in funding earlier this year”. (And a followup article here.)

A couple years ago, an EDA synthesis friend of mine, Karen Pieper, moved on from Synopsys to a startup called Tabula. It was all very secret until now, at least from me, but this week there’s a sudden flurry of articles about Tabula, including an article in the local Silicon Valley newspaper. Now I can finally see what Karen’s been working on, and it looks good.

According to Steve Meier

Tabula space time architecture, time based multiplexing = large increase in density, #EDA will be key

According to Ron Wilson in “Tabula FPGAs: this one could be game-changing“.

Instead of putting a single set of interconnect muxes, a LUT, and a latch in each logic cell, Tabula puts in eight of everything. Then they time-domain multiplex those eight sets of hardware on a 1.6 GHz master clock, so that the physical logic cell has a whole new personality—new interconnect routing, new LUT, and new latch configuration—every 600ps. Over the course of 5ns, the physical logic cell is, in effect, eight different logic cells.

[…] Tabula embeds transparent latches in the interconnect where it passes through the physical cell, and controls these latches with the time-multiplexing circuitry as well. So on each clock cycle, Tabula captures the state of the interconnect and logic cell in the latches. This allows the chip to pass the output of the LUT, for instance, to the input of the same or a nearby physical LUT on the next clock cycle. All the state that goes in flight during an eight-cycle sequence is available to drive cells on subsequent cycles. It is almost as if the FPGA had eight times as many logic cells as it actually does.

And, finally, below in the comments section, Shalom Bresticker provided the link to a Tabula white paper with plenty of graphics.



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