Multiple inheritance and SystemVerilog

Update2: Intel proposal on “interface classes for multiple inheritance” — LINK.

Update1: Intel on multiple inheritance — LINK.

According to Dave Rich in his paper “The Problems with Lack of Multiple Inheritance in SystemVerilog and a Solution”

The concept of multiple class inheritance is a feature that many Object-Oriented Programming (OOP) languages have where a subclass can inherit behaviors (i.e. class methods and properties) from more than one superclass. As the language is currently defined, a SystemVerilog subclass (child class) can only extend from a single superclass (parent class). This paper presents some of the problems of having an OOP language lacking multiple inheritance, and then suggests a solution.


Finally, this paper recommends a solution for SystemVerilog by introducing the concept of a class interface, similar in nature to a virtual class with pure virtual methods. Multiple superclass interfaces could be extended as the base of a single subclass. Examples are presented to show the potential for reduced code complexity and improved performance.

Dave presented this paper at DVCon 2010. For more about Dave, see his blog.


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