Accellera-sponsored DAC update on what’s new in SystemVerilog 2009

Update: The PRESENTATIONS are archived HERE and HERE. They describe dozens of new enhancements.

The following is just to explain the context of the presentations archived above.

I received the following information from Cliff Cummings

SystemVerilog Is Getting Even Better!
An Update on the Proposed 2009 SystemVerilog Standard, sponsored by Accellera
Tuesday, July 28, 2009
1:30pm – 2:30pm
Moscone Convention Center Room 309

Abstract:
Verification and design engineering teams worldwide have rapidly
adopted the SystemVerilog-2005 standard and found SystemVerilog to
be beneficial for delivering working, well tested products in an
efficient and timely manner. The IEEE SystemVerilog standards group
has continued to improve SystemVerilog, based on feedback and
requests from engineers who are using the standard, and from
companies implementing SystemVerilog tools. This presentation
provides an overview of more than 50 major new features being added
in the proposed SystemVerilog-2009 standard. Many of these new
features are substantial, and improve the ability to accurately and
efficiently model and verify extremely complex digital designs. The
presenters are Cliff Cummings of Sunburst Design and Stuart
Sutherland
of Sutherland HDL. Both presenters are experts in
SystemVerilog and are renown for providing dynamic and informative
presentations and tutorials. DON’T MISS THIS OPPORTUNITY! If you
are involved with IC design and/or verification in any way, you will
enjoy and benefit from attending this important update on the
SystemVerilog standard!

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