SystemVerilog 2009 goes to ballot — 18/Feb thru 20/March

The ballot for the 2009 revision of the IEEE SystemVerilog standard opens today (18/Feb/2009) and will continue for a month until the end of 20/March/2009.

It is likely that after the P1800 committee has responsed to ballot comments, a revised draft will be recirculated and there will be a second ballot, probably beginning early in June.

The status regarding the patent disclosure notice from Mentor Graphics remains unchanged.


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