SystemVerilog subtypes

An annoyance of SystemVerilog is that there’s no way to declare a subtype of the non-class types, for example, a T that is like integer, except that it’s constrained to [-128,128).

Should it be possible to create subtypes by declaring constraints on non-class types?

      typedef integer T;

      constraint C { T inside {[-128,127]};

Or maybe the syntax could be part of the typedef by adding, say, a with clause to typedef, such as,

     typedef integer T with ( -128 <= T && T < 128);

or, less generally, maybe just as an inside clause

     typedef integer T inside {[-128,127]};

It would still need to be defined what happens when such a constraint is violated — something like the deferred immediate assertions or uniquecase?


Tell me (anonymous OK)

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