In SystemVerilog arrays of interfaces are in some ways more powerful than generate

In Verilog (and SystemVerilog), there are two ways to declare an indexed collection of instances – arrays of instances and generate.

SystemVerilog extended arrays of instances in two ways

1) Arrays of instances can be multidimensional.

2) Arrays of (interface) instances can be connected to a port.

So in SystemVerilog, arrays of instances are in some ways more powerful than generate, because generate can’t be used to declare a truly multidimensional collection of instances or to declare a collection of (interface) instances that can be connected to a port.

The root of the difference is that with generate, although each instance in the indexed collection has a name, the collection itself has no name. An individual generated (interface) instance can be connected to a port, but, because there is no way to refer to the collection as a whole, there is no way to connect that collection to a port.

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2 Comments

  1. I added arrays of instances to Verilog because we didn’t have time to get generate before release OVI 1.0 in 1990. From my experience, arrays of instances covered 90% of applications that would have used generate. That’s why there wasn’t much pressure to get them added to 1364-1995.

    Dave

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