SystemVerilog and unconstrained array types

Amal Khailtash writes

I still cannot believe that functions with unconstrained arrays as their input or  output is not supported (specifically for synthesis). There are many different situations that I would like to write some generic code that is reused among many blocks.  I understand that one might be able to write it as a parameterized module instead of a function call.  But I still believe a generic function call would be a much more natural view of a problem.



The mult example was just to give an example. This is simple enough that can be done with operators. My intention is to use functions for more complicated operations. CRC, LFSR, different Encoder/Decoders, …. Defining these and other functions with fixed size is not practical. Even if one returns a larger size and takes only the bits needed is not a good practice. I need reusable, generic  functions that can be synthesized. I guess I have to stick to VHDL  for this. Even though Verilog2001/SystemVerilog were touted to have everything VHDL has and even more.

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