SystemVerilog 2009 design enhancements

See here for my complete list of the likely SystemVerilog 2009 design enhancements.  (Disclaimer: All of these are subject to change until after the balloting process is completed, but I doubt they will actually change much.)

Associated with each item is a link  into a publicly readable database.  The proposals are in the Attached Files sections.

Some highlights

  • default parameter values optional
  • selects on (concatenated) expressions, e.g., {a+b}[4:0]
  • logical equivalence (<->) and implication (->) operators
  • default values for macro args
  • default input values for module/interface ports
  • 0-delay-glitch-free semantics of unique/unique0/priority case/if
  • ‘let’ name binding construct
  • package import declarations in module/interface headers

To me, ‘let’ is the most interesting of these. For example, you could use it to add a ‘rot(v,n)’ syntax for barrel shifting ‘v’ by ‘n’

let rot(v, n) = {2{v}} << n >> $bits(v);

Here’s an example combining ‘let’ and selects on expressions.  Suppose you want to select bits from an expression that evaluates to a bit-stream type , but not a packed type, as required for selects on expression.  Define a ‘let’ to bit-stream cast them into a simple bit-vector type

let pack (x) = type($bits(x)'(0))'(x) ;

and select away, for example

{ pack(expression) } [N-1:0]

And to force an arithmetic expression to be evaluated in a self-determined context, you could use the following ‘let’

let selfd(x) = type(x)'(x) ;

FYI — there are also some significant enhancements to the assertions sublanguage.

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