True 3D chips will require reversible logic
There are still many ways to decrease the energy dissipated by computer chips, such as asynchronous design styles. But until we transcend the Landauer limit with reversible computing, we’ll be stuck in 2D, because heating scales as the volume, but cooling only scales as the surface area.
According to Joe Fitzsimons
The rate at which a region of space can be cooled scales as the surface area, where as the heat produced scales as the number of irreversible gates. For a 2D array these scale in the same way, but for a 3D array the heating scales as the volume (R^3) where as the cooling scales as the surface area of a bounding box (R^2). Clearly you need to balance the rate at which heat is produced with the rate at which it is removed, and hence you have a scaling problem with 3D arrays. This is entirely independent of the cooling mechanism.
According to Greg Kuperberg
Transistors in real computers are not very far away from melting. Even though many computers look 3-dimensional, most of the geometry of a computer is within each chip of the computer, and that geometry is almost completely 2-dimensional. One reason for that is the photolithography used to make the chips. But another reason is that there is no way to carry away the heat from a 3-dimensional block of transistors. Without that problem you could sandwich many chips together in a sort-of 3-dimensional pile. The heat problem effectively limits real computers to the power of 2-dimensional cellular automata. However, this 2-dimensional geometry is mostly used to simulate a RAM machine. It cannot be an efficient simulation, but it is what happens in practice, since most higher-level languages create a RAM machine environment for software. It’s also a pain to design algorithms for a 2D computational grid rather than for a RAM machine.